Enum PortClass 

pub enum PortClass {
    Conducting,
    ControlInput,
    Transducer(Domain),
    Rail,
}

Device-agnostic classification of what a single port (a component.pin) is, derived entirely from existing model facts — no new annotation.

Variants

Conducting

An ordinary current-conducting terminal that gets MNA/WDF-stamped: a tube plate / cathode, BJT collector / emitter, R/C/L pins, op-amp output. The default for anything that is not a control / transducer / rail port.

ControlInput

A high-impedance signal-control electrode: tube grid, BJT base, FET gate, op-amp inverting/non-inverting input. Derived from SignalTerminals::Amplifier input/control.

Transducer(Domain)

A transducer port that couples across a non-electrical Domain (photocoupler .led, OTA .iabc, VCA .cv, FET .vgs). Derived from Component::modulation_sink.

Rail

A supply / ground / AC-ground rail node. Derived from the graph rail sets. (A node property; from_component cannot see it, so it is supplied by PortClass::from_pin_in_graph.)

Implementations

impl PortClass

pub fn from_component(comp: &dyn Component, pin: &str) -> Self

Derive the class of pin on comp from the device model alone.

This is the component-fact half of the derivation (it cannot see graph nodes, so it never returns PortClass::Rail — use PortClass::from_pin_in_graph for the rail-aware classification).

Precedence (most-specific first):

1. A pin that is a Component::modulation_sink is a transducer port — .led, .iabc, .cv, .vgs. (A FET’s vgs/gate IS a transducer port when read this way; that is the intended unification — the control electrode of an externally-modulated device is a transducer.)
2. A pin that is the input or control of an SignalTerminals::Amplifier is a PortClass::ControlInput — grid / base / gate / op-amp pos+neg.
3. Otherwise PortClass::Conducting.

pub fn from_pin_in_graph( comp: &dyn Component, pin: &str, node: usize, graph: &CircuitGraph, ) -> Self

Rail-aware classification of comp.pin resolved against graph.

Identical to PortClass::from_component except a pin whose resolved node is a rail (gnd / vcc / named supply / AC-ground) returns PortClass::Rail. The rail check takes precedence because a terminal tied straight to a rail is electrically a rail port regardless of its device role.

pub fn label(self) -> &'static str

Human-readable label for diagnostics.

Trait Implementations

impl Clone for PortClass

fn clone(&self) -> PortClass

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for PortClass

impl Debug for PortClass

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Eq for PortClass

impl Hash for PortClass

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl PartialEq for PortClass

fn eq(&self, other: &PortClass) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl StructuralPartialEq for PortClass