Enum GraphRole 

pub enum GraphRole {
    Edge {
        pin_a: &'static str,
        pin_b: &'static str,
    },
    ActiveEdge {
        pin_a: &'static str,
        pin_b: &'static str,
    },
    CoupledEdge {
        edge_pin_a: &'static str,
        edge_pin_b: &'static str,
        coupled_pins: &'static [&'static str],
    },
    Pot,
    Transformer,
    Virtual,
    ActiveIc,
    VcvsEdge {
        pin_pos: &'static str,
        pin_neg: &'static str,
        pin_out: &'static str,
    },
}

How a component participates in circuit graph construction.

Variants

Edge

Creates one edge between two named pins.

Fields

pin_a: &'static str

pin_b: &'static str

ActiveEdge

Creates one edge AND counts as an active element.

Fields

pin_a: &'static str

pin_b: &'static str

CoupledEdge

Creates one edge with multi-terminal coupling (tubes). edge_pin_a → edge_pin_b is the WDF edge. coupled_pins lists ALL pins that should be coupled for BFS traversal.

Fields

edge_pin_a: &'static str

edge_pin_b: &'static str

coupled_pins: &'static [&'static str]

Pot

Potentiometer: 2-terminal or 3-terminal depending on wiper usage in nets.

Transformer

Transformer: complex multi-winding handling (aliases, coupling, center taps).

Virtual

No circuit edge, not active (LFO, EnvelopeFollower, BBD, control elements).

ActiveIc

No circuit edge, but counts as active (OpAmp, VCO, VCF, etc.).

VcvsEdge

Op-amp / finite-gain VCVS: three pins (pos, neg, out) participate in the circuit graph as junction nodes. Produces no WDF-tree edge but is absorbed as a VCVS stamp into the MNA matrix of its containing R-type adaptor (Werner 2016 nullor, generalised to finite Aol and Ro).

The three pins are registered in CircuitGraph::nullor_pins so the R-type stage builder can emit one MnaSystem::stamp_vcvs per op-amp with the appropriate datasheet parameters.

Fields

pin_pos: &'static str

pin_neg: &'static str

pin_out: &'static str