Struct Lfo 

pub struct Lfo {
    pub waveform: LfoWaveformDsl,
    pub timing_r: f64,
    pub timing_c: f64,
}

Fields

waveform: LfoWaveformDsl

timing_r: f64

timing_c: f64

Trait Implementations

impl Clone for Lfo

fn clone(&self) -> Lfo

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Component for Lfo

fn clone_box(&self) -> Box<dyn Component>

Clone into a boxed trait object.

fn as_any(&self) -> &dyn Any

Downcast to Any for type-erased equality checks and downcasting.

fn as_any_mut(&mut self) -> &mut dyn Any

Downcast to Any mutably for in-place mutation (e.g., tolerance tweaks).

fn dyn_eq(&self, other: &dyn Component) -> bool

Dynamic equality: returns true if other is the same concrete type and compares equal.

fn type_tag(&self) -> &'static str

Human-readable type name (e.g. “resistor”, “NPN transistor”).

fn is_passive(&self) -> bool

Whether this component is passive (collectible by BFS for stage building).

fn pin_config(&self) -> PinConfig

Valid pins and aliases for this component type.

fn graph_role(&self) -> GraphRole

How this component participates in circuit graph construction.

fn stamp_mna( &self, _comp_id: &str, _n1: Option<usize>, _n2: Option<usize>, _mna: &mut MnaSystem, _sample_rate: f64, ) -> StampResult

Stamp into MNA system. Returns what was produced.

fn validate_values(&self, comp_id: &str) -> Vec<(Severity, String)>

Check for suspicious or invalid component values.

fn controls(&self) -> Vec<ControlParam>

Declare controllable parameters for this component.

fn footprint_ref(&self) -> (&'static str, &'static str)

KiCad symbol library reference and designator prefix.

fn symbol_name(&self) -> &'static str

Symbol identifier for layout rendering (e.g., “resistor”, “triode”, “opamp”).

fn layout_class(&self) -> &'static str

Layout class identifier for placement grouping (e.g., “resistor”, “npn”, “opamp”).

fn is_modulation_source(&self) -> bool

fn solver_hint(&self) -> Option<SolverMethod>

Return the preferred nonlinear solver method for this component.

fn ports(&self) -> Vec<(&'static str, &'static str)>

Terminal pairs carrying current through this component.

fn nonideal_fx(&self, _sample_rate: f64) -> Vec<NonIdealFx>

Non-ideal behaviors for this component (GBW, slew, rails, thermal, etc.).

fn output_impedance(&self) -> OutputImpedance

Output impedance at this component’s output pin.

fn signal_terminals(&self) -> SignalTerminals

Signal flow classification for this component’s pins.

fn port_semantic(&self, _pin_a: &str, _pin_b: &str) -> PortSemantic

Classify the electrical behavior of a port (pin pair) for optimization legality checks. The compiler uses this to determine which subgraphs can be safely lowered to IIR/BlackFeedback vs requiring full MNA/WDF.

fn is_nonlinear(&self) -> bool

Whether this component is a nonlinear element (needs NR solver).

fn is_active_ic(&self) -> bool

Whether this component is an active IC (counted toward num_active).

fn is_control_only(&self) -> bool

Whether this component is a control-only element (no circuit pins).

fn is_variable(&self) -> bool

Whether this component’s edge impedance changes at runtime. Stages containing variable edges need scattering matrix recomputation.

fn modulation_pins(&self) -> &'static [&'static str]

Extra pins that are valid as modulation targets but may not be in pin_config.

fn edges(&self) -> Vec<ComponentEdge>

Declare this component’s circuit edges with their electrical classification.

fn signal_adjacencies(&self) -> Vec<(&'static str, &'static str)>

Internal signal-path adjacencies: pin pairs that signal can traverse through.

fn pin_direction(&self, _pin: &str) -> PinDirection

Infer the signal direction for a given pin on this component.

fn resolve_edges( &self, _neighbors: &ResolveContext, ) -> Option<Vec<ComponentEdge>>

Context-dependent resolution: if this component’s behavior depends on how it’s wired, return a new edge list reflecting the resolved role.

fn mna_vsource_count(&self) -> usize

Number of MNA voltage sources this component needs when stamped into an R-node. Default: 0. Op-amps return 1 (for the VCVS constraint).

fn mna_internal_node_count(&self) -> usize

Number of internal MNA nodes this component needs. Default: 0. Op-amps return 1 (internal gain stage node for GBW pole).

fn stamp_mna_multi( &self, comp_id: &str, ctx: &mut StampContext<'_>, mna: &mut MnaSystem, ) -> StampResult

Stamp this component into an MNA system using multi-terminal pin resolution.

fn make_leaf(&self, _comp_id: &str, _sample_rate: f64) -> Option<DynNode>

Create a WDF leaf node for this component. Returns None for non-leaf components (diodes, virtual elements, etc.).

fn resistance(&self) -> Option<f64>

fn capacitance(&self) -> Option<f64>

fn inductance(&self) -> Option<f64>

fn terminal_requirements(&self) -> Vec<(&'static str, Vec<NeighborReq>)>

Per-terminal neighbour requirements for active devices.

fn classify_nonlinear( &self, _comp_id: &str, _node_a: usize, _node_b: usize, _gnd_node: usize, _node_names: &HashMap<String, usize>, ) -> Option<(NonlinearKind, Vec<usize>)>

Classify this component as a nonlinear element for the circuit solver.

fn modulation_sink(&self, _pin: &str) -> Option<ModulationSink>

If this component can be a modulation sink (LFO/envelope target), return the sink description for the given pin.

fn is_bjt(&self) -> bool

fn is_jfet(&self) -> bool

fn is_mosfet(&self) -> bool

fn is_tube(&self) -> bool

fn is_transformer(&self) -> bool

fn is_pot(&self) -> bool

fn is_diode_family(&self) -> bool

fn is_trigger(&self) -> bool

fn feedback_input_is_barrier(&self) -> bool

Whether this element’s input node acts as a summing junction that should block BFS traversal in the signal flow graph.

fn k_method_spec(&self) -> Option<KMethodSpec>

K-method table shape declared by the component.

fn k_method_candidacy(&self) -> (bool, usize, &'static str)

Compatibility wrapper for callers that still only need yes/no + dimensionality. New code should prefer Component::k_method_spec because it preserves the meaning of each table axis.

fn is_simple_passive(&self) -> bool

Passive two-terminal element (R, C, L, etc.) — excludes transformers and pots.

fn is_gain_device(&self) -> bool

Amplifying device: tube, BJT, JFET, MOSFET.

fn model_name(&self) -> Option<&str>

fn op_amp_type(&self) -> Option<OpAmpType>

fn pot_taper(&self) -> Option<PotTaper>

fn diode_type(&self) -> Option<DiodeType>

fn transformer_config(&self) -> Option<&TransformerConfig>

fn apply_bias( &self, _bias_voltages: &HashMap<String, f64>, _supply_voltage: f64, ) -> BiasResult

Apply DC bias from a static bias network detected at compile time.

fn display_value(&self) -> Option<String>

Human-readable display value for labels (e.g., “4.7kΩ”, “100nF”).

impl Debug for Lfo

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq for Lfo

fn eq(&self, other: &Lfo) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl StructuralPartialEq for Lfo